A field effect transistor (FET) has an undoped or very lightly doped channel region disposed between heavily doped source and drain regions. When the gate length of a field effect transistor (FET) is very small, there is danger that source and drain dopants will diffuse into the channel during high-temperature processing steps, potentially shorting the channel.
This problem is particularly acute when multiple stacked device levels are formed above a substrate in monolithic three dimensional memory arrays, as in Walker et al., U.S. Pat. No. 7,005,350, “Method for Fabricating Programmable Memory Array Structures Incorporating Series-Connected Transistor Strings.” In such a stacked array, each memory level may be subjected to repeated high-temperature steps, each causing more unwanted dopant diffusion.
There is a need, therefore, for a method to form a transistor, particularly a stackable thin film transistor, with minimal dopant diffusion.